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Hardware: Add 20GB modding guide, cmp-pstate NVAPI tool, and document private NvAPI_GPU_SetForcePstate and PCIe retrain mechanisms

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wmantly
2026-09-02 00:02:24 +00:00
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@@ -99,10 +99,23 @@ Comparing the hardware profiles and the cross-flashing outcome:
## 8. 20GB VRAM Modding Feasibility (CMP 50HX TU102)
* **Architecture**: CMP 50HX uses the **TU102 PCB layout (320-bit bus, 10 memory pads)**.
* **Memory Swap**:
* Desolder 10x 1GB (8Gbit) GDDR6 BGA-180 chips (e.g., Samsung `K4Z80325BC-HC14`).
* Solder 10x 2GB (16Gbit) GDDR6 BGA-180 chips (e.g., Samsung `K4ZAF325BM-HC14` or Micron `D9ZCL`).
* Modify memory strapping resistor dividers to signal 16Gbit density to the TU102 memory controller.
* **Payoff**:
* 2x Modded Cards = **40 GB Total VRAM** (capable of running full 70B/72B models like `Llama-3.3-70B` or `Qwen2.5-72B` on just 2 dedicated x16 slots).
* **Hardware Swap**: Desolder 10x 1GB (8Gbit) GDDR6 BGA-180 chips and replace with 10x 2GB (16Gbit) chips (e.g., Samsung `K4ZAF325BM-HC14` or Micron `D9ZCL`). Adjust memory strapping resistor dividers.
* **Driver Patching for 20GB (WPR2 Fix)**: See [`docs/20GB_MOD_GUIDE.md`](20GB_MOD_GUIDE.md) for details on patching the NVIDIA open kernel driver to bypass the `0x8d` FWSEC error.
* **Capacity Scaling**:
* 2x Modded Cards = **40 GB Total VRAM** (runs full 70B/72B models on 2 slots).
* 4x Modded Cards = **80 GB Total VRAM** (enterprise A100-tier capacity for under $1,000).
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## 9. Private NVAPI `NvAPI_GPU_SetForcePstate` (`0x025BFB10`)
* **The Discovery**: While `nvidia-smi` cannot force P8 state on headless Linux, the private NVAPI entry point `NvAPI_GPU_SetForcePstate` (`0x025BFB10`) inside `libnvidia-api.so.1` can explicitly force the GPU into **P8 state (645 MHz core / 405 MHz memory)**.
* **Implementation**: We packaged [`tools/cmp-pstate.py`](../tools/cmp-pstate.py) to directly invoke this entry point per PCI Bus ID.
* **Restoration**: Passing `--pstate 16` returns power management control to unconstrained P0/P3 states before active inference.
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## 10. Automated PCIe Link Retraining Service (`cmp50hx-gen2`)
* **The Boot Lock**: CMP 50HX cards feature an internal PCIe speed lock register that takes a short period after boot to become accessible.
* **The Solution**: A systemd boot service triggers a link retrain on the upstream PCIe port after boot, ensuring the bus reliably trains at full speed without manual re-initialization.