56 lines
4.5 KiB
Markdown
56 lines
4.5 KiB
Markdown
# 🌐 The CMP Reverse Engineering & Hardware Modding Landscape
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An exhaustive overview of the community, firmware reverse engineering, driver unlocks, and physical hardware modifications turning crippled NVIDIA CMP mining cards into high-performance AI inference workstations.
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## 🗺️ Key Repositories & Lineage
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| Project | Focus Cards | Technique & Core Breakthrough | Notes |
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| :--- | :--- | :--- | :--- |
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| **[`pearlfortune/cmpunlocker`](https://github.com/pearlfortune/cmpunlocker)** | 50HX, 90HX, 170HX | **Stockflow Method**: Patches the NVIDIA Open Kernel Driver (`610.43.03`) to un-throttle SM compute and issue rates. | The foundational multi-card open-source unlocker. |
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| **[`xrip/cmp50hx-unlock`](https://github.com/xrip/cmp50hx-unlock)** | 50HX (TU102) | **Full SM + Tensor + ReBAR 16GB + PCIe Gen2 + 20GB VRAM mod + NVAPI Idle Governor**. | Best-documented 50HX repository; proven dynamic FWSEC WPR2 handling for 20GB memory swaps. |
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| **`WildFlash1st` / `bendy2` / `jdowning100`** | 90HX (GA102) | **"Rejoin" Technique**: Injects PLM register opens directly after `GFW_BOOT`. | Huge prefill gains (7–8x throughput boost reported). |
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| **`Icyoung/cmpunlocker`** | 90HX, 70HX | **Graphics / Raster Unlock**: Attempts to restore the GR graphics engine for 3D/Vulkan rendering. | Focused on desktop and display restoration. |
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| **`Cyridd/cmpunlocker`** | 50HX | **Userspace `libnvidia-eglcore` patching**: Removes Vulkan pipeline-bind throttles. | Userspace library binary modification. |
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## 🔬 How the Silicon Unlocks Work
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NVIDIA intentionally crippled CMP mining GPUs at multiple levels to prevent them from competing with GeForce and Quadro cards:
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1. **SM Compute Issue Rate Throttling**: The firmware artificially caps instruction dispatch per warp. The *Stockflow* and *Rejoin* patches intercept driver initialization to open the `GFX_SPEED_SELECT` and PLM registers, restoring 100% full CUDA and Tensor core throughput.
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2. **PCIe Speed & ReBAR Limits**: The BIOS locks the PCIe link target speed register at boot. A timed link retrain (`cmp50hx-gen2`) after the initial boot window forces the upstream port to negotiate full bandwidth.
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3. **Signed Firmware Barriers (FWSEC / GSP-RM)**: Rather than attempting to bypass cryptographic signatures on the VBIOS ROMs, the community reverse engineers how the driver hands off memory bounds to the signed GSP-RM, dynamically calculating the `0xe00` WPR2 span to allow physical 20GB memory expansions.
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## 🛠️ Physical Hardware Modding Scene
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### 1. The 20GB VRAM Swap (TU102)
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* **The Mod**: Replacing the ten 1GB (8Gbit) GDDR6 BGA-180 chips with 2GB (16Gbit) chips (Samsung `K4ZAF325BM-HC14` or Micron `D9ZCL`).
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* **Strapping Resistors**: Moving SMD pull-up/pull-down resistor dividers near the memory controller to configure the hardware address lines for 16Gbit density.
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* **Driver Patch**: Running the dynamic WPR2 patch on the NVIDIA open kernel module (`610.43.03`) prevents the `error 0x8d` boot crash.
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* **Result**: Dual 20GB CMP 50HX cards give **40 GB Total VRAM**—enough to run full 70B parameter models (`Llama-3.3-70B`, `Qwen2.5-72B`) locally on a budget rig.
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### 2. PCIe x16 Lane Restoration
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* Some CMP boards have physical PCIe traces present on the PCB but lack the SMD AC coupling capacitors for lanes 5–16.
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* Soldering 0.1µF 0402 ceramic capacitors across the missing lane pads restores full x16 electrical lane width on compatible motherboards.
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## 👥 Communities & Provenance
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* **Reverse Engineering Hubs**: Active Russian (Habr / dartraider) and Chinese hardware modification circles on Telegram and private forums.
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* **HiveOS & Mining Heritage**: Much of the underlying low-level register mapping originated from mining enthusiasts who were extracting maximum hash efficiency before transitioning to AI inference.
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* **Hardware Modder Videos**: Detailed BGA rework tutorials on Russian and Chinese YouTube/Bilibili channels showing exact microscopic resistor strap positions and thermal profiles.
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## 💡 Why This Matters for Local AI
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Most of the tech world views CMP cards as discarded mining e-waste. In reality, a modded CMP 50HX is a **TU102 silicon die (same chip as the RTX 2080 Ti and Titan RTX)** with 3,584 CUDA cores, FP16/INT8 Tensor cores, and a 320-bit memory bus:
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* **Cost**: ~$100–$150 per card + memory chips.
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* **VRAM**: 20 GB GDDR6 per card.
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* **Cluster Capacity**: 3 to 4 cards deliver **60 GB to 80 GB of unified VRAM** at full NCCL tensor-parallel speed for a fraction of the cost of a single enterprise A100/H100 GPU.
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