🌐 The CMP Reverse Engineering & Hardware Modding Landscape

An exhaustive overview of the community, firmware reverse engineering, driver unlocks, and physical hardware modifications turning crippled NVIDIA CMP mining cards into high-performance AI inference workstations.

🗺️ Key Repositories & Lineage

Project	Focus Cards	Technique & Core Breakthrough	Notes
`pearlfortune/cmpunlocker`	50HX, 90HX, 170HX	Stockflow Method: Patches the NVIDIA Open Kernel Driver (`610.43.03`) to un-throttle SM compute and issue rates.	The foundational multi-card open-source unlocker.
`xrip/cmp50hx-unlock`	50HX (TU102)	Full SM + Tensor + ReBAR 16GB + PCIe Gen2 + 20GB VRAM mod + NVAPI Idle Governor.	Best-documented 50HX repository; proven dynamic FWSEC WPR2 handling for 20GB memory swaps.
`WildFlash1st` / `bendy2` / `jdowning100`	90HX (GA102)	"Rejoin" Technique: Injects PLM register opens directly after `GFW_BOOT`.	Huge prefill gains (7–8x throughput boost reported).
`Icyoung/cmpunlocker`	90HX, 70HX	Graphics / Raster Unlock: Attempts to restore the GR graphics engine for 3D/Vulkan rendering.	Focused on desktop and display restoration.
`Cyridd/cmpunlocker`	50HX	Userspace `libnvidia-eglcore` patching: Removes Vulkan pipeline-bind throttles.	Userspace library binary modification.

🔬 How the Silicon Unlocks Work

NVIDIA intentionally crippled CMP mining GPUs at multiple levels to prevent them from competing with GeForce and Quadro cards:

SM Compute Issue Rate Throttling: The firmware artificially caps instruction dispatch per warp. The Stockflow and Rejoin patches intercept driver initialization to open the GFX_SPEED_SELECT and PLM registers, restoring 100% full CUDA and Tensor core throughput.
PCIe Speed & ReBAR Limits: The BIOS locks the PCIe link target speed register at boot. A timed link retrain (cmp50hx-gen2) after the initial boot window forces the upstream port to negotiate full bandwidth.
Signed Firmware Barriers (FWSEC / GSP-RM): Rather than attempting to bypass cryptographic signatures on the VBIOS ROMs, the community reverse engineers how the driver hands off memory bounds to the signed GSP-RM, dynamically calculating the 0xe00 WPR2 span to allow physical 20GB memory expansions.

🛠️ Physical Hardware Modding Scene

1. The 20GB VRAM Swap (TU102)

The Mod: Replacing the ten 1GB (8Gbit) GDDR6 BGA-180 chips with 2GB (16Gbit) chips (Samsung K4ZAF325BM-HC14 or Micron D9ZCL).
Strapping Resistors: Moving SMD pull-up/pull-down resistor dividers near the memory controller to configure the hardware address lines for 16Gbit density.
Driver Patch: Running the dynamic WPR2 patch on the NVIDIA open kernel module (610.43.03) prevents the error 0x8d boot crash.
Result: Dual 20GB CMP 50HX cards give 40 GB Total VRAM—enough to run full 70B parameter models (Llama-3.3-70B, Qwen2.5-72B) locally on a budget rig.

2. PCIe x16 Lane Restoration

Some CMP boards have physical PCIe traces present on the PCB but lack the SMD AC coupling capacitors for lanes 5–16.
Soldering 0.1µF 0402 ceramic capacitors across the missing lane pads restores full x16 electrical lane width on compatible motherboards.

👥 Communities & Provenance

Reverse Engineering Hubs: Active Russian (Habr / dartraider) and Chinese hardware modification circles on Telegram and private forums.
HiveOS & Mining Heritage: Much of the underlying low-level register mapping originated from mining enthusiasts who were extracting maximum hash efficiency before transitioning to AI inference.
Hardware Modder Videos: Detailed BGA rework tutorials on Russian and Chinese YouTube/Bilibili channels showing exact microscopic resistor strap positions and thermal profiles.

💡 Why This Matters for Local AI

Most of the tech world views CMP cards as discarded mining e-waste. In reality, a modded CMP 50HX is a TU102 silicon die (same chip as the RTX 2080 Ti and Titan RTX) with 3,584 CUDA cores, FP16/INT8 Tensor cores, and a 320-bit memory bus:

Cost: ~$100–$150 per card + memory chips.
VRAM: 20 GB GDDR6 per card.
Cluster Capacity: 3 to 4 cards deliver 60 GB to 80 GB of unified VRAM at full NCCL tensor-parallel speed for a fraction of the cost of a single enterprise A100/H100 GPU.

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